The present invention relates to semiconductor devices and methods for fabricating the devices, and more particularly relates to semiconductor devices which have a MIM (metal-insulator-metal) capacitor and a resistor for use in an analog circuit, e.g., and a method for fabricating the semiconductor devices.
MIM capacitors which have a dielectric film between an upper capacitor electrode and a lower capacitor electrode, or resistors are often incorporated as passive elements into a semiconductor integrated circuit device in which analog circuits are laid out.
FIG. 9 is a cross sectional view illustrating the structure of a conventional MIM capacitor used in integrated analog circuits.
Shown in FIG. 9 is an example of a conventional MIM capacitor device used in semiconductor integrated analog circuits, where a lower capacitor electrode 101a and a first interconnect 101b, both of which are made of a first conductive film 101, are formed on a first insulating layer 100 fabricated over a semiconductor substrate (not shown), and an inner surface of a large opening 102a formed in a second insulating layer 102 is covered by a dielectric film 103 serving as the MIM insulator, and an upper capacitor electrode 104a made of a second conductive film 104 is formed over the dielectric film 103 while an inner surface of a contact hole 102b formed through the second insulating film 103 to the first interconnect 101b is covered by the second conductive film 104 to form a second interconnect 104b so as to constitute an ordinary two-level interconnect system.
FIG. 10 is a cross sectional view of the structure of a MIM capacitor different from the structure shown in FIG. 9, which illustrates a typical MIM capacitor which employs planarized W plug contacts in a semiconductor integrated circuit. In particular, in a large scale integration circuit (LSI) semiconductor having submicron devices, a planarized structure such as shown in FIG. 10 is adopted to achieve improved process capabilities of lithographic patterning steps, which otherwise would be affected by un-planarized surface topology.
As shown in FIG. 10, a first interconnect 201 is formed on an insulating film 200 formed on a semiconductor substrate (not shown.) On the first interconnect 201 serving as a lower capacitor electrode, a dielectric film 202 and an upper capacitor electrode 203 are formed in sequence from downward. Contacts 205a and 205b filled by a W film and planarized are formed in an insulating film 204 to connect to the upper capacitor electrode 203 and the first interconnect 201, respectively. Over the planarized W plug contacts 205a and 205b, second interconnects 206a and 206b, both made of a second conductive film 206, are formed on the insulating film 204 to form electrical connections to the upper capacitor electrode 203 and the lower capacitor electrode 201, respectively.
FIG. 11 is a cross sectional view illustrating a resistor typically used in an analog circuit in a semiconductor integrated device.
As shown in FIG. 11, an insulating film 301 for device-isolation is formed on a Si substrate 300, and a polysilicon resistor 302 of a high impurity concentration is formed on the insulating film 301, and an insulating film 303 is formed over the polysilicon resistor 302 and the insulating film 301, and contact holes 304 formed through the insulating film 303 to the polysilicon resistor 302 are filled by a W film and planarized to form W plug contacts to the polysilicon resistor 302, and second interconnects 305 are formed to make electrical connections to the polysilicon resistor 302 via the contacts 304, (See Japanese Laid-Open Publication Nos. 62-42553, 01-223757, and 2001-203329, for example.)
To form the MIM capacitor illustrated in FIG. 9, the following steps may be carried out: forming the lower capacitor electrode 101a and the first interconnect 101b, both of which are made of the first conductive layer 101 constituting a lower level of a multilevel interconnect system in the semiconductor integrated circuit; forming the upper capacitor electrode 104a and the second interconnect 104b, both of which are made of the second conductive film 104 constituting an upper level of the multilevel interconnect system in the semiconductor integrated circuit; and in addition, forming the opening 102a for forming the capacitor in the insulating film 102 and depositing the dielectric film 103. In this case, as can be seen in FIG. 9, the contact 102c formed of the second conductive film 104 on the first interconnect 10b, and the second interconnect 104b made of the second conductive film 104 are formed in the following manner. After the dielectric film 103 is deposited on the opening 102a and the insulating film 102, the contact hole 102b is formed. Next, the second interconnect layer 104 is deposited on the contact hole 102b and the dielectric film 103, and then patterned, whereby the second interconnect 104b is formed over the first interconnect 101b with the contact 102c being interposed therebetween.
Due to this structure, the following problem arises. In a densely packed LSI, the size of the contact hole 102c is submicron and the contact hole 102c have to be filled by a refractory metal film such as a W film which must be planarized by CMP (Chemical Mechanical Polishing) and etchback to form a plug contact. However, the W film formed over the large opening 102a are easily removed by the planarization techniques such as CMP and etchback, and thus the structure of FIG. 9 is not compatible with a modern submicron-device fabricating process.
In view of this, in recent years, MIM capacitors such as shown in FIG. 10 become more favorable in fabricating densely packed LSI of the submicron feature size. Nevertheless, formation of MIM capacitors having such a structure requires the process steps of depositing the dielectric film 202, depositing a metal layer which forms the upper capacitor electrode 203, and patterning the metal layer to form the upper capacitor electrode 203. After the dielectric film 202 and the upper capacitor electrode 203 have been patterned, the first interconnect 201 serving as the lower capacitor electrode is patterned. This puts a limit on the thickness of a photoresist film used in photolithographically patterning the first interconnect 201 as the lower capacitor electrode, if the difference in level, which is equal to the film thickness of the upper capacitor electrode 203, is taken into account. Furthermore, since the thickness of the insulating film 204 differs between where the insulating film 204 is on the upper capacitor electrode 203 and where it is on the first interconnect 201, the reliability of the contact 205b formed on the first interconnect 201 and the second interconnect 206b is reduced because the depth of the contact hole 205b is deeper than that of the contact hole 205a so that there exists a higher probability of having inadequate filling of the W film in the contact hole 205b. 
Also, since the resistor shown in FIG. 11 is formed out of a polysilicon film which is used in a gate-electrode formation process, for example, the value of the resistor becomes higher than necessary to form an analog circuit, and varies considerably. Therefore, in a device having a structure in which a resistor and a circuit are directly connected, or having a multilayer interconnect structure inbetween, if the interconnect length from the circuit to the resistor has to be long, the parasitic resistance is increased, causing a problem in that the parasitic resistance affects the resistor value.